The present invention relates to a layout method, a layout system, and a non-transitory computer readable medium storing a layout program of a semiconductor integrated circuit, and more specifically, to a layout method, a layout system, and a non-transitory computer readable medium storing a layout program of a semiconductor integrated circuit to execute timing analysis based on arrangement wiring information of a sequential circuit.
In recent years, power consumption in layout design has been increasing due to an increase in size of a semiconductor integrated circuit including an ASIC (Application Specific Integrated Circuit), a micon, and an ASSP (Application Specific Standard Produce). Further, influences of OCV (On Chip Variation) are spread along with miniaturization of the process of the semiconductor integrated circuit. Further, an increase in size of the semiconductor integrated circuit makes timing convergence difficult due to the degradation of CTS (Clock Tree Synthesis) skew, which increases design TAT (Turn Around Time). Accordingly, there has been an increasing demand to decrease an area of the layout in the semiconductor integrated circuit, decrease power consumption, and further reduce an OCV value and a CTS skew value.
Japanese Unexamined Patent Application Publication No. 2000-348083 discloses a technique related to a layout method and a layout device of a semiconductor integrated circuit that are capable of suppressing an increase in the layout area and power consumption by reducing skew of the CTS. According to the layout method and the layout device disclosed in Japanese Unexamined Patent Application Publication No. 2000-348083, FFs are re-arranged so that the wiring length of each FF in the CTS final stage becomes an average wiring length distance. Accordingly, insertion of the Delay cell to match the CTS can be suppressed, thereby reducing an area in laying out the semiconductor integrated circuit, power consumption, and OCV target distance.
FIG. 10 is a flow chart showing a process flow of a layout method of a semiconductor integrated circuit according to Japanese Unexamined Patent Application Publication No. 2000-348083. First, a layout device X (not shown) of the semiconductor integrated circuit according to Japanese Unexamined Patent Application Publication No. 2000-348083 arranges FFs that are the layout target (S91). Next, the layout device X arranges and wires the arranged FFs by CTS (S92). This is the normal CTS process.
FIG. 11 is a diagram showing an example of a circuit diagram after CTS process in the layout method of the semiconductor integrated circuit according to Japanese Unexamined Patent Application Publication No. 2000-348083. In the following description, the FF group including the CTS final stage buffer is called a CTS block. In FIG. 11, a CTS block 91 includes a buffer 910 which is a CTS final stage buffer, and FFs 911 to 913 clock-wired from the buffer 910. A CTS block 92 includes a buffer 920 which is a CTS final stage buffer, and FFs 921 to 923 that are clock-wired from the buffer 920. The CTS block includes the CTS blocks 91 to 9n (n is an integer of three or larger).
In this case, the layout device X selects the longest wiring length from the CTS final stage buffer to the FF for each CTS block (S93). For example, the layout device X selects a wiring length L1 from the buffer 910 to the FF 912 as the longest wiring length in the CTS block 91. Further, the layout device X selects a wiring length L2 from the buffer 920 to the FF 921 as the longest wiring length in the CTS block 92. Hereinafter, similarly, the layout device X selects a wiring length Ln from the buffer 9n0 to the FF 9n3 as the longest wiring length in the CTS block 9n. 
Then, the layout device X calculates an average value L using the longest wiring length selected in each CTS block (S94). In summary, the layout device X calculates an average value Lavg of the longest wiring length according to the following expression (1).(L1+L2+ . . . +Ln)/n=Lavg  (1)
Subsequently, the layout device X re-arranges the FF in the coordinate (x, y) that satisfies the following expression (2) (S95). Specifically, the layout device X re-arranges each FF on sides of the square that satisfies the expression (2) in the two-dimensional coordinate of the x axis and the y axis with the origin of the CTS final stage buffer in each CTS block.L=|x|+|y|  (2)
Then, the layout device X wires the CTS final stage buffer to each FF that is re-arranged with the minimum distance for each CTS block (S96). Specifically, the layout device X wires the CTS final stage buffer of the origin to each FF by combinations of straight lines parallel to the x axis or the y axis. Accordingly, in Japanese Unexamined Patent Application Publication No. 2000-348083, the wiring length from the final stage buffer to each FF is made closer to the distance of the average wiring length.
FIG. 12 is a diagram describing a concept of arrangement in the layout method of the semiconductor integrated circuit according to Japanese Unexamined Patent Application Publication No. 2000-348083. In the CTS block 91, the lengths of the wiring from the buffer 910 to each of the FFs 911, 912, and 913 shown in solid lines are equal to one another. Similarly, in the CTS block 92, the lengths of the wiring from the buffer 920 to each of the FFs 921, 922, and 923 shown in solid lines are equal to one another.
FIG. 13 is a diagram describing a concept of arrangement in the layout method of the semiconductor integrated circuit according to Japanese Unexamined Patent Application Publication No. 2000-348083. It is assumed that, at origin, a CTS final stage buffer in one CTS block is arranged. Then, the points of average values Lavg of the longest wiring length in the positive and negative directions on the x axis and the y axis are denoted by a, b, c, and d. Connecting the points a, b, c, and d by a dotted line with these points as apices gives a square. The square can be expressed using the expression (2) when a coordinate on a side of the square is expressed by (x, y). Further, L in the first quadrant to the fourth quadrant can be expressed as the following expressions (21) to (24).(First quadrant) L=x+y  (21)(Second quadrant) L=−x+y  (22)(Third quadrant) L=−x−y  (23)(Fourth quadrant) L=x−y  (24)
For example, when the FF is arranged in the point B (x1, y1) shown in FIG. 13 and wired from the CTS final stage buffer which is the origin with the path of O-A-B, the wiring length is expressed by the following expression (3).OA+AB=x1+y1=Lavg  (3)
Similarly, when the FF is arranged in the point E (x2, y2) shown in FIG. 13 and wired from the CTS final stage buffer which is the origin with the path of O-C-D-E, the wiring length is expressed by the following expression (4).OC+CD+DE=(OC+DE)+CD+DE)+CD=|x2|+|y2|=Lavg  (4)
Then, the layout device X executes rough wiring (S97), detailed wiring (S98), and verification (S99).